• From: Tokyo, Japan
  • Registered: 2009-01-19
  • Posts: 3

Topic: JTAG lands on main board

Hello.

I have a few questions about JTAG lands on the circuit board. My circuit board is "Ironforge v1.8A", and it seems to have two kinds of JTAG lands. The one is "P600" for CP. And the other is "P100" next to the "P600". But it has no information about details except for documented as "CPU JTAG" on the silkscreen.

Does anybody know the answers of following questions?

1) Is it the lands for i.MX21?
2) Does anybody know its pin assignment?
3) Is it possible to use JTAG for debugging the programs for i.MX21?

Thanks in advance.

  • From: Singapore
  • Registered: 2006-08-26
  • Posts: 188

Re: JTAG lands on main board

The P100 surface-mount lands are for the CPU (i.MX21). They are "embedded" inside the CP JTAG footprint, hence the confusion.

The pinout of P100 is as follows:

1 - 3.3V
2 - TCK
3 - TDI
4 - GND
5 - TMS
6 - TDO
7 - TRST
8 - CHUMBY_RESET

There is a bar on the silkscreen that denotes pin 1.

You will need to solder on a connector and use a flex cable, plus an adapter board to use this JTAG connector (or just solder fly wires on to whatever JTAG headers are required).

Yes, it is possible to use the JTAG for debugging programs for the i.MX21. We haven't done this in chumby, but Freescale does provide support for this and there are several third-party JTAG devices that will interoperate with chumby. Keep in mind to check for Linux (or at least post-virtual memory mapping) support on the JTAG debug software package.

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  • From: Tokyo, Japan
  • Registered: 2009-01-19
  • Posts: 3

Re: JTAG lands on main board

Thanks for replying so quickly, bunnie.

I'll give it a try. I'm going to use the JTAG "YOKOGAWA advicePRO ZX600" and its additional library for Linux debugging.

  • From: Tokyo, Japan
  • Registered: 2009-01-19
  • Posts: 3

Re: JTAG lands on main board

Hi.

I connected the JTAG to the "P100" according to the directions above, but it didn't work well. I observed the signals with an oscilloscope, and I found the problem in my environment.

I wired the "SRST" signal of the JTAG ICE to "CHUMBY_RESET", and it seemed to be going well for the JTAG ICE to control the CPU reset. But the "CHUMBY_RESET" didn't change to 0 volt, when the "SRST" was asserted by the JTAG ICE. It declined to about 1.2 volt instead. Therefore the JTAG ICE couldn't reset i.MX21.

I guess it might be due to the connection with CP usually negating.

There is no information about that connection on the schematics. So, I want to know about the situation of it.

Is there "OR" logic ( actually, it's "AND" logic due to "active low" ) between "CHUMBY_RESET of P100" and "CHUMBY_RESET of CP's I/O port P1.13" ?

Thanks in advance.